Image processor capable of edge enhancement in saturated region

ABSTRACT

An image processing device includes a data zone expansion circuit and an image processing circuit. The data zone expansion circuit receives input data, increases a number of data bits of the input data, and provides data with the increased number of data bits. The image processing circuit performs image processing on the data with the increased number of data bits.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application number09/737,502, filed Dec. 18, 2000, pending.

[0002] This application is based upon and claims the priority ofJapanese application no. 2000-041393, filed Feb. 15, 2000, and U.S.patent application Ser. No. 09/737,502, filed Dec. 18, 2000, thecontents being incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention relates to an image processor incorporatedin a display device such as a flat panel display device or a CRT displaydevice, or connected to a display device.

[0005] 2. Description of the Related Art

[0006] It has been required to improve image quality by processingdigital image signals, in company with increase, in processing speed ofan LSI.

[0007]FIG. 8 is a schematic block diagram showing a prior art imagedisplay device.

[0008] Digital image signals of three primary colors R, G and B areprovided to respective image processing circuits 10R, 10G and 10B toperform filtering processing such as edge enhancement, and the resultsthereof are provided through a display control circuit 12 to an LCDpanel 14 to display pictures on the panel 14. The display controlcircuit 12 includes a multi-port VRAM and a control circuit therefor.

[0009] However, as shown in FIG. 9, when an edge enhancement processingis followed by clipping in regions where pixels are saturated at themaximum value MAX0 or the minimum value no effect of the edgeenhancement processing can be achieved.

SUMMARY OF THE INVENTION

[0010] Accordingly, it is an object of the present invention to providea image processor capable of effectively performing an image processingsuch as an edge enhancement processing even in a region of saturatedpixel values, with a simple construction.

[0011] In one aspect of the present invention, there is provided animage processing circuit comprising: a data zone expansion circuit,receiving input data X, expanding a data zone of the input data bylinearly converting X to (αX+β), where α and β are given values,providing the data-zone expanded data (αX+β); and an image processingcircuit, performing image processing on the data-zone-expanded data(αX+β).

[0012] In the prior art, when an edge enhancement processing is appliedon image data, an image processing effect such as edge enhancement couldnot be achieved in pixel value

[0013] saturated regions at the maximum or minimum value. Such an effectcan be achieved with this aspect having a simple construction that thedata zone expansion circuit is provided at the preceding stage of theimage processing circuit, thereby contributing to improvement in imagequality.

[0014] Other aspects, objects, and the advantages of the presentinvention will become apparent from the following detailed descriptiontaken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a schematic block diagram showing an image displaydevice of a first embodiment according to the present invention;

[0016]FIG. 2 is a block diagram showing an embodiment of the data zoneexpansion circuit of FIG. 1;

[0017]FIG. 3 is a block diagram showing an embodiment of the data zonecontraction circuit of FIG. 1;

[0018]FIG. 4 is a graph showing a result of data zone expansion on dataof FIG. 9, wherein an abscissa represents a pixel position on a displayline and an ordinate represents a pixel value;

[0019]FIG. 5 is a graph showing a result of an edge enhancementprocessing on data of FIG. 4;

[0020]FIG. 6 is a graph showing a result of data zone contraction ondata of FIG. 5;

[0021]FIG. 7(A) is a block diagram showing a data zone expansion circuitemployed in an image processor of a second embodiment according to thepresent invention;

[0022]FIG. 7(B) is a block diagram showing a data zone contractioncircuit employed in this image processor;

[0023]FIG. 8 is a schematic block diagram showing a prior art imagedisplay device; and

[0024]FIG. 9 is a graph showing an example of image data from which noeffect is achieved even after an edge enhancement processing thereforwith the display device of FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Referring now to the drawings, wherein like reference charactersdesignate like or corresponding parts throughout several views,preferred embodiments of the present invention are described below.

First Embodiment

[0026]FIG. 1 is a schematic block diagram showing an image displaydevice of a first embodiment according to the present invention.

[0027] Digital image signals in three primary colors R, G and B areprovided to data zone expansion circuits 16R, 16G and 16B, respectively.

[0028] The data zone expansion circuit 16R linearly converts an inputsignal R in a range of 0 to MAX0 to an output signal (αX R+β), in arange of 0 to MAX1 in order to

[0029] accommodate the output signal with sufficient upper and lowermargins. Herein, MAX1 >MAX0, and α and β are constants satisfyingconditions of α>1 and , β≧0. For simplification of a circuit, generally,α=2^(n), n is a positive integer and a is 0 or a positive integer.

[0030] For example, the input signal R is a signal as shown in FIG. 9having a pixel position on a display line as a time axis, and isconverted to a signal shown in FIG. 4.

[0031] The minimum value 0 and the maximum value MAX0 of the inputsignal R are converted to β and αX MAX0+β, respectively, and thefollowing relation holds in order to accommodate the output signal withsufficient upper and lower margins.

[0032] 0<β<αX MAX0+<MAX1

[0033] That is, the converted minimum value , and the converted maximumvalue (αX MAX0 +β) are within an output data range of 0 to MAX1.

[0034]FIG. 2 shows an embodiment of the data zone expansion circuit 16R.

[0035] The data zone expansion circuit 16R includes an adder 161 and anoffset register 161.

[0036] Assume that the input signal R has 8 bits R7 to R0. A first datainput of the adder 161 is of 9 bits, and the R7 to R0 bits are providedto the higher 8 bits D8 to D1 thereof while ‘0’ is provided to thelowest one bit D0. That is, α=2. The second data input of the adder 161is, for example, of 4 bits, and the output a of the offset register 162is provided to the second data input. A data output of the adder 161 isof 9 bits and an output of the data zone expansion circuit 16R is 10bits having the 9 bits of the output and a carry bit C of the adder 161.In this case, the output data length of the data zone expansion circuit16R is 10 bit for the input 8 bits.

[0037] This applies to cases of the data zone expansion circuits 16G and16B in a similar manner.

[0038] Corresponding outputs from the data zone expansion circuits 16R,16G and 16B are provided to image processing circuits 20R, 20G and 20B,respectively.

[0039] The image processing circuit 20R differs from the imageprocessing circuit 10R of FIG. 8 in that a word length of a pixel valueto be processed is larger than that of the input signal R. In the imageprocessing circuit 20R, a filtering processing is performed such as edgeenhancement or interpolation accompanying zoom in or out of an image.For example, when an edge enhancement processing is performed on imagedata shown in FIG. 4 by the image processing circuit 20R, data shown inFIG. 5 is obtained as a result.

[0040] This applies to cases of the image processing circuits 20G and20B in a similar manner.

[0041] A display control circuit 12 and an LCD panel 14 have the sameconstructions as those of FIG. 8. Therefore, data zone contractioncircuits 18R, 18G and 18B are connected between the respective imageprocessing circuits 20R, 20G and 20B and the display control circuit 12,and perform the inverse of processing of the data zone expansioncircuits 16R, 16G and 16B.

[0042]FIG. 3 shows an embodiment of the data zone contraction circuit18R.

[0043] The data contraction circuit 18R includes a subtracter 181 and anoffset register 182.

[0044] An output RI of the image processing circuit 20R is of 10 bitsand provided to a first data input of the subtracter 181. The seconddata input of the subtracter 181 is, for example, of 4 bits and theoutput β of the offset register 182 is provided to the other data input.The carry C of the subtracter 181 is not used as one bit of the outputof the data zone contraction circuit 18R. The output data of thesubtracter 181 is of 9 bits D08 to D00 and the higher 8 bits D08 to D01are of:the output D0=(RI−β)/α of the data zone contraction circuit 18R.

[0045] This applies to cases of the data zone contraction circuits 18Gand 18B in a similar manner.

[0046] For example, the data of FIG. 5 having a pixel position on adisplay line as a time axis is provided to the data zone contractioncircuit 18R, and is converted to a signal shown in FIG. 6.

[0047] In the prior art, when an edge enhancement processing isperformed on image data shown in FIG. 9, no effect of edge enhancementis achieved in saturated regions at the minimum value and the maximumvalue of pixels, while the effect can be achieved according to the firstembodiment, leading to improvement on the image quality.

[0048] As a result of experiments, in a case where the input signals R,G and B are all of 8 bits and the word length of the output data of thedata expansion circuit 16R is of 10 bits, the above described effect ofthe edge enhancement is able to be achieved when β=2 for the offsetregisters 162 and 182.

[0049] According to the first embodiment, it has a simple constructionin which the data zone expansion circuit 16R and the data zonecontraction circuit 18R are provided at stages before and after theimage processing circuit 20R, respectively, and the image processing canbe performed even in the pixel value saturated regions with improvedimage quality.

Second Embodiment

[0050]FIG. 7(A) shows a data zone expansion circuit 16RA employed in animage processor of a second embodiment according to the presentinvention.

[0051] The circuit 16RA includes a 9 bit up-counter. The output of thedata zone expansion circuit 16RA has a parallel output obtained byproviding one pulse of a clock to the clock input CK after a parallelinput R7 to R0 is loaded on the counter, and an added lowest bit “0”.The output is 2(R+1)=2R+2 for the input R. That is, α=2 and β=2.

[0052]FIG. 7(B) shows a data zone contraction circuit 18RA employed inthe image processor of the second embodiment according to the presentinvention.

[0053] The data zone contraction circuit 18RA includes a 10 bitdown-counter. A parallel input R19 to R10 is loaded on the counter, 2pulses of the clock 0 are provided to the clock input CK thereof, andthe output of the data zone contraction circuit 18R is obtained from anintermediate 8 bit parallel output D08 to D01 excluding LSB and MSBamong 10 bits. The output is (RI−2)/2 for the input RI. That is, α=2 andβ=2.

[0054] The other points-are the same as those of the first embodiment.

[0055] Although preferred embodiments of the present invention has beendescribed, it is to be understood that the invention is not limitedthereto and that various changes and modifications may be made withoutdeparting from the spirit and scope of the invention.

[0056] Please note that various other kinds of modifications oralterations can be included in the present invention.

[0057] For example, there may be adopted a construction in which thedata zone contraction circuit is omitted in FIG. 1.

[0058] Further, a linear transformation in the data zone contractioncircuit is not limited to the inversion of the processing of the datazone expansion circuit. Accordingly, the output word length of the datazone contraction circuit may be different from the input word length ofthe data zone expansion circuit.

[0059] Furthermore, The value of β set in the offset register may bedetermined according to a lightness or a chroma of image. Fixed valuesmay be provided to the adder 16 and the subtracter 181 without using theoffset registers.

What is claimed:
 1. An image processing method comprising the steps or:receiving input data; increasing a number of data bits of said inputdata: performing image processing on said data with the increased numberof data bits, wherein said image processing includes enhancing an edgeof said data with the increased number of data bits; decreasing a numberof the image-decreased data; and providing data having a number of databits substantially the same as said received input data.
 2. The imageprocessing method of claim 1, further comprising the step of increasingthe number of data bits of said input data by multiplying said inputdata by a constant value and adding an offset value to said input data,wherein a word length of said data with the increased number of databits is larger than that of said input data.
 3. The image processingmethod of claim 1, further comprising the step of decreasing the numberof data bits of said image-processed data by subtracting an offset valuefrom said image-processed data and dividing the result of thesubtracting by a constant value, wherein a word length of the data withthe decreased number of data bits is smaller than that of saidimage-processed data.
 4. The image processing method of claim 2, furthercomprising the step of decreasing the number of data bits of saidimage-processed data by subtracting an offset value from saidimage-processed data and dividing the result of the subtracting by aconstant value, wherein a word length of the data with the decreasednumber of data bite is smaller than that of said image-processed data.